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AD9135BCPZRL

数模转换器- DAC Dual 11-b 2.8Gsps DAC 10.6GbpsJESD204B

Product Details

The AD9135 is a dual, 11-bit, high dynamic range digital-to-analog converter DAC that provides a maximum sample rate of 2800 MSPS, permitting a multicarrier generation over a very wide bandwidth. The DAC outputs are optimized to interface seamlessly with the ADRF6720, as well as other analog quadrature modulators AQMs from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface SPI provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a typical range of 13.9 mA to 27.0 mA. The AD9135 is available in an 88-lead LFCSP.

**Product Highlights**

1. Greater than 2 GHz, ultrawide complex signal bandwidth enables emerging wideband and multiband wireless applications.

2. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.

3. JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design.

4. Fewer pins for data interface width with a serializer/deserializer SERDES JESD204B eight-lane interface.

5. Programmable transmit enable function allows easy design balance between power consumption and wake-up time.

6. Small package size with 12 mm × 12 mm footprint.

**Applications**

.
Wireless communications
.
3G/4G W-CDMA base stations
.
Wideband repeaters
.
Software defined radios
.
Wideband communications
.
Point to point
.
Local multipoint distribution service LMDS and multichannel multipoint distribution service MMDS
.
Transmit diversity, multiple input/multiple output MIMO
.
Instrumentation
.
Automated test equipment

### Features and Benefits

.
Support input data rate >2 GSPS
.
Proprietary low spurious and distortion design
.
SFDR = 82 dBc at dc IF, −9 dBFS
.
Flexible 8-lane JESD204B interface
.
Multiple chip synchronization
.
Fixed latency
.
Data generator latency compensation
.
Selectable 1×, 2×, 4×, or 8× interpolation filter
.
Low power architecture
.
Transmit enable function allows extra power saving and instant control of the output status
.
High performance, low noise phase-locked loop PLL clock multiplier
.
Digital inverse sinc filter
.
Low power: 1.42 W at 1.6 GSPS full operating conditions
.
88-lead LFCSP with exposed pad

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