STA5620CTR

GPS Receiver 1.57542GMHz 3.3V 32Pin VFQFPN EP T/R

The chip is a fully integrated RF front-end able to down-convert the GPS L1 signal from 1575.42 MHz to 4.092 MHz.

The IF signal is converted by a two bit ADC. Sign SIGN, Magnitude MAG and the 16.368 MHz sampling clock GPS_CLK are provided to the baseband.

The magnitude data is internally integrated in order to control the variable gain amplifiers in accordance to the RF input signal strength.

An excellent quality of reception in critical environments is ensured by the good noise figure and linearity of the receiver.

The on-chip oscillator supports crystal frequencies in the range of 10 MHz to 40 MHz. It is able to support TCXO providing also a buffered copy of the oscillator frequency.

The chip, using STMicroelectronics BiCMOS SiGe technology, is housed in a QFN-32 package.

**Key Features**

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Low IF architecture fIF = 4fO

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Minimum external components

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VGA gain internally regulated

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On chip programmable PLL

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Typ. 2.7 V supply voltage

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SPI interface

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2 kV HBM ESD protected

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Compatible with GPS L1

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Standard QFN-32 package

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Low power for portable designs