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CHIP SET INTERFACE SPECIFICATION

DESCRIPTION

The goal of this document is to provide a Hardware / Software interface specifications of the FPGA component Xilinx SPARTANXL XCS40XL-4PQ208C used in the STMicroelectronics Contactless System. The FPGA manages the communication between the MCU and the Analog Front End. This component formats the frames in accordance with ISO 14443 type B standard.

PHYSICAL INTERFACE BETWEEN FPGA AND MCU

This corresponds to a classical memory interface between bidirectional Data bus, Selection signal, Read/Write signal and a signal used to select either FIFOs or Control/Status registers access

Interface signals description

In order to simplify interface specification, the FPGA logic has been designed with the same accesses for FIFOs and Control Registers. This is the reason why the read access chronogram show only one access type figure 1

However, for write access chronogram, two access types are shown figures 2 & 3.

MCU accesses are done in burst mode for the FIFOs, it is not useful to generate addresses. So, there is no address bus for the MCU Interface. To address the different control registers, the two MSB bits from the data bus must be used.

These control registers have to be setted during the first transmission each time the code is down loaded in FPGA start up of the reader or when any parameter has to be modified. For later transmissions, the control registers don’t need to be re initialised.

The control Register Description is available in table 2.