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CY7C1061G30-10BV1XI

SRAM Chip Async Single 2.5V/3.3V 16M-bit 1M x 16 10ns 48Pin VFBGA

* High speed: tAA = 10 ns/15 ns * Low active and standby currents * Icc = 90-mA typical at 100 MHz * Isb2 = 20-mA typical * Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and4.5 V to 5.5 V * 1.0-V data retention * Transistor-transistor logic TTL compatible inputs and outputs * Error indication ERR pin to indicate 1-bit error detection andcorrection * Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages


立创商城:
CY7C1061G30-10BV1XI


得捷:
NO WARRANTY


贸泽:
SRAM 16Mb Fast SRAM With ECC


艾睿:
SRAM Chip Async Single 2.5V/3.3V 16M-bit 1M x 16 10ns 48-Pin VFBGA Tray


安富利:
CY7C1061G is high-performance CMOS fast static RAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. To access devices with a single chip enable input, assert the chip enable CE\\ input LOW. To access dual chip enable devices, assert both chip enable inputs - CE1\ as LOW and CE2 as HIGH. To perform data writes, assert the Write Enable WE\\ input LOW, and provide the data and address on the device data pins I/O0 through I/O15 and address pins A0 through A19 respectively. The Byte High Enable BHE\\ and Byte Low Enable BLE\\ inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE\ controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable OE\\ input and provide the required address on the address lines. Read data is accessible on I/O lines I/O0 through I/O15. You can perform byte accesses by asserting the required byte enable signal BHE\ or BLE\\ to read either the upper byte or the lower byte of data from the specified address location. All I/Os I/O0 through I/O15 are placed in a high-impedance state when the device is deselected CE\ HIGH for a single chip enable device and CE1 HIGH / CE2 LOW for a dual chip enable device, or control signals are de-asserted OE\, BLE\, BHE\\.


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