PC82573L

Ethernet CTLR Single Chip 10Mbps/100Mbps/1000Mbps 1.2V/2.5V/3.3V 196Pin TFBGA

Introduction

Unless specifically noted, 82573 refers to the ® 82573E, 82573V and 82573L GbE controllers.

82573 GbE controllers are single, compact components with integrated Gigabit Ethernet Media Access Control MAC and Physical Layer PHY functions. These devices use PCIe

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architecture Revision 1.0a. For desktop, workstation, and value server network designs with critical space constraints, the 82573 enables a GbE implementation in a very small area.

The 82573 provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications 802.3, 802.3u, and 802.3ab, respectively. In addition to managing MAC and PHY Ethernet layer functions, the 82573 manages PCIe

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packet traffic across its transaction, link, and physical and logical layers.

Product Features

PCIe

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   — x1 PCIe

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interface on ICH7 or MCH devices

   — Peak bandwidth: 2 Gb/s per direction

   — Power management

   — High bandwidth density per pin

MAC

   — Optimized transmit and receive queues

   — IEEE 802.3x compliant flow control with software controlled pause times and threshold values

   — Caches up to 64 packet descriptors per queue

   — Programmable host memory receive buffers 256 bytes to 16 KB and cache line size 16 bytes to 256 bytes

   — 32 KB configurable transmit and receive FIFO buffer

   — Mechanism available for reducing interrupts generated by transmit and receive operation

   — Descriptor ring management hardware for transmit and receive

   — Optimized descriptor fetching and write-back mechanisms

   — Wide, pipelined internal data path architecture

PHY

   — Integrated PHY for 10/100/1000 Mb/s full and half duplex operation

   — IEEE 802.3ab auto negotiation support

   — IEEE 802.3ab PHY compliance and compatibility

   — DSP architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation

Host Offloading

   — Transmit and receive IP, TCP and UDP checksum off-loading capabilities

   — Transmit TCP segmentation, IPv6 offloading, and advanced packet filtering

   — IEEE 802.1q VLAN support with VLAN tag insertion, stripping and packet filtering for up to 4096 VLAN tags

   — Descriptor ring management hardware for transmit and receive Order Number: 315514-002

Manageability

   — Intel® Active Management Technology Intel® AMT support 82573E only

   — Alerting Standards Format 2.0 and advanced pass through support 82573E/V only

   — Boot ROM Preboot eXecution Environment PXE Flash interface support

   — Compliance with PCI Power Management 1.1 and Advanced Configuration and Power Interface ACPI 2.0 register set compliant

   — Wake on LAN support

Additional

   — Three activity and link indication outputs that directly drive LEDs

   — Programmable LEDs

   — Internal PLL for clock generation that can use a 25 MHz crystal

   — Power saving feature for the 82573L. During the L1 and L2 link states, the 82573L asserts the Clock Request signal CLKREQ# to indicate that its PCIe

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reference clock can be gated

   — On-chip power control circuitry

   — Loopback capabilities

   — JTAG IEEE 1149.1 Test Access Port TAP built in silicon

Technology

   — Lead-free 196-pin Thin and Fine Pitch Ball Grid Array TF-BGA package

   — Operating temperature: 0° C to 70° C with external regulators

   — Operating temperature: 0° to 55° C with on die 2.5V regulator

   — Storage temperature -40° C to 125° C