74HCT164N

移位寄存器, 串行至并行, 1元件, DIP, 14 引脚, 4.5 V, 5.5 V

The is a 8-bit serial-in/parallel-out Shift Register features two serial data inputs DSA and DSB, eight parallel data outputs Q0 to Q7. Data is entered serially through DSA or DSB and either input can be used as an active high enable for data entry through the other input. Data is shifted on the low-to-high transitions of the clock CP input. A low on the master reset input MR clears the register and forces all outputs low, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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TTL Level

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Gated serial data inputs

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Asynchronous master reset

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Complies with JEDEC standard No. 7A