74ALVCF322835GX

总线收发器 Bus Driver LV 36Bit Universal

The 74ALVCF322835 low voltage 36-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable OE#, latch-enable LE, and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs I

n

to Outputs O

n

on a Positive Edge Transition of the Clock. When OE# is LOW, the output data is enabled. When OE# is HIGH the output port is in a high impedance state. The 74ALVCF322835 is designed with 26ohm series resistors in the outputs. This design reduces noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The 74ALVCF322835 is designed for low voltage 1.65V to 3.6V V

CC

applications with I/O capability up to 3.6V

Product Highlights

Compatible with PC133 DIMM module specifications

1.65V to 3.6V V

CC

specifications provided

3.6V tolerant outputs

26ohm series resistors in outputs

t

PD

CLK to O

n

3.7 ns max for 3.0V to 3.6V V

CC

4.6 ns max for 2.3V to 2.7V V

CC

7.4 ns max for 1.65V to 1.95V V

CC

Power-down high impedance outputs

Latchup conforms to JEDEC JED78

ESD performance:

Human body model > 2000V

Machine model >200V