TPS51206DSQT

TEXAS INSTRUMENTS  TPS51206DSQT  芯片, 稳压器, LDO, 固定, 1.2V, 2A, SON-10

The is a sink and source double date rate DDR Termination Regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage and low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 x 10µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 DDR3L VTT bus. The VTT current capability is ±2A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state suspend to RAM and discharging VTT and VTTREF in S4/S5 state suspend to disk.

.

Supports 3.3V rail and 5V rail supply input voltage

.

VTT + 0.4 to 3.5V VLDOIN input voltage range

.

0.5 to 0.9V Output voltage range

.

2A Peak sink and source current

.

±20mV Accuracy

.

VTTREF Buffered reference - VDDQ/2 ±1% accuracy, 10mA sink/source current

.

Overtemperature protection

.

Green product and no Sb/Br