SM32C6415EGLZ50AEP

定点数字信号处理器 FIXED-POINT DIGITAL SIGNAL PROCESSORS

* Highest-Performance Fixed-Point Digital Signal Processors DSPs * 2-ns Instruction Cycle Time * 500-MHz Clock Rate * Eight 32-Bit Instructions/Cycle * 28 Operations/Cycle * 4000 MIPS * Fully Software Compatible With C62x™ * C6414/15/16 Devices Pin Compatible * Veloci.2™ Extensions to VelociTI™ Advanced Very Long Instruction Word VLIW TMS320C64x™ DSP Core * Eight Highly Independent Functional Units With VelociTI.2 Extensions With Six ALUs and Two Multipliers * Nonaligned Load-Store Architecture * 64 32-Bit General-Purpose Registers * Instruction Packing Reduces Code Size * All Instructions Conditional * Instruction Set Features * Byte-Addressable 8-/16-/32-/64-Bit Data * 8-Bit Overflow Protection * Bit-Field Extract, Set, Clear * Normalization, Saturation, Bit-Counting * VelociTI.2 Increased Orthogonality * Viterbi Decoder Coprocessor VCP C6416 * Supports Over 500 7.95-Kbps Adaptive Multi-Rate AMR * Programmable Code Parameters * Turbo Decoder Coprocessor TCP C6416 * Supports up to Six 2-Mbps 3GPP 6 Iterations * Programmable Turbo Code and Decoding Parameters * L1/L2 Memory Architecture * 128K-Bit 16K-Byte L1P Program Cache * 128K-Bit 16K-Byte L1D Data Cache * 8M-Bit 1024K-Byte L2 Unified Mapped RAM/Cache * Two External Memory Interfaces EMIFs for 1280M-Byte Addressable External Memory * Enhanced Direct-Memory-Access EDMA Controller 64 Independent Channels * Host-Port Interface HPI * User-Configurable Bus Width 32/16 Bit * 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 C6415/C6416 * Three PCI Bus Address Registers * Four-Wire Serial EEPROM Interface * PCI Interrupt Request Under DSP Program Control * DSP Interrupt Via PCI I/O Cycle * Three Multichannel Buffered Serial Ports McBSPs * Direct Interface to T1/E1, MVIP, SCSA Framers * Up to 256 Channels Each * ST-Bus-Switching, AC97-Compatible * Serial Peripheral Interface SPI Compatible Motorola * Three 32-Bit General-Purpose Timers * Universal Test and Operations Physical Layer PHY Interface for ATM UTOPIA C6415/C6416 * UTOPIA Level 2 Slave ATM Controller * 8-Bit Transmit and Receive Operations up to 50 MHz per Direction * User-Defined Cell Format up to 64 Bytes * Sixteen General-Purpose I/O GPIO Pins * Flexible Phase-Locked Loop PLL Clock Generator * IEEE-1149.1 JTAG1 Boundary-Scan-Compatible * 532-Pin Ball Grid Array BGA Package GLZ Suffix, 0.8-mm Ball Pitch * 0.13-µm/6-Level Metal Process CMOS * 3.3-V I/Os, 1.25-V Internal 500 MHz * SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS * Controlled Baseline * One Assembly/Test Site * One Fabrication Site * Available in A-Version –40°C/105°C and S-Version –55°C/105°C Temperature Ranges2 * Extended Product Life Cycle * Extended Product-Change Notification * Product Traceability