HEF4094BT

NXP  HEF4094BT  移位寄存器, 1元件, SOIC, 16 引脚, 4.5 V, 15.5 V

The is a 8-stage serial Shift Register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe STR input is high. Data in the storage register appears at the outputs whenever the output enable OE signal is high. Two serial outputs QS1 and QS2 are available for cascading a number of HEF4094B devices. Serial data is available at QS1 on positive going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading HEF4094B devices when the clock has a slow rise time.

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Fully static operation

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Standardized symmetrical output characteristics

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Complies with JEDEC standard JESD 13-B