ADS54J66IRMP

四通道、14 位、500MSPS 模数转换器 ADC 72-VQFN -40 to 85

The ADS54J66 is a low-power, wide-bandwidth, 14-bit, 500-MSPS, quad-channel, telecom receiver device. The ADS54J66 supports a JESD204B serial interface with data rates up to 10 Gbps with one lane per channel. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. The ADS54J66 provides excellent spurious-free dynamic range SFDR over a large input frequency range with very low power consumption. The digital signal processing block includes complex mixers followed by low-pass filters with decimate-by-2 and -4 options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of interface lines, thus allowing high system integration density. An internal phase locked loop PLL multiplies the incoming analog-to-digital converter ADC sampling clock to derive the bit clock, which is used to serialize the 14-bit data from each channel.