MT48LC16M4A2TG-75

Synchronous DRAM, 16MX4, 5.4ns, CMOS, PDSO54, 0.4INCH, PLASTIC, TSOP2-54

SYNCHRONOUS DRAM

MT48LC16M4A2  – 4 Meg x 4 x 4 banks

MT48LC8M8A2  – 2 Meg x 8 x 4 banks

MT48LC4M16A2  – 1 Meg x 16 x 4 banks

FEATURES

• PC66-, PC100-, and PC133-compliant

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

• Self Refresh Modes: standard and low power

• 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply