AD7193

4通道， 4.8千赫，超低噪声， 24位Σ -Δ型ADC， PGA 4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA

GENERAL DESCRIPTION

The is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta Σ-Δ analog-to-digital converter ADC. The on-chip low noise gain stage means that signals of small amplitude can interface directly to the ADC.

FEATURES

Fast settling filter option

4 differential/8 pseudo differential input channels

RMS noise: 11 nV @ 4.7 Hz gain = 128

15.5 noise-free bits @ 2.4 kHz gain = 128

Up to 22 noise-free bits gain = 1

Offset drift: ±5 nV/°C

Gain drift: ±1 ppm/°C

Specified drift over time

Automatic channel sequencer

Programmable gain 1 to 128

Output data rate: 4.7 Hz to 4.8 kHz

Internal or external clock

Simultaneous 50 Hz/60 Hz rejection

4 general-purpose digital outputs

Power supply

  AVDD: 3 V to 5.25 V

  DVDD: 2.7 V to 5.25 V

Current: 4.65 mA

Temperature range: −40°C to +105°C

Package: 28-lead TSSOP

Interface

   3-wire serial

   SPI, QSPI™, MICROWIRE™, and DSP compatible

  Schmitt trigger on SCLK

APPLICATIONS

PLC/DCS analog input modules

Data acquisition

Strain gage transducers

Pressure measurement