SN74ACT74DRG4

具有清零和预置端的双路正边沿触发式 D 型触发器 14-SOIC -40 to 85

description/ordering information

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset PRE or clear CLR input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive high, data at the data D input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

• 4.5-V to 5.5-V VCC Operation

• Inputs Accept Voltages to 5.5 V

• Max tpd of 10.5 ns at 5 V

• Inputs Are TTL-Voltage Compatible