万年历中年的VHDL程序

一、 纪年的程序：
闰年2月为29天，平年为28天。闰年的确定是年份的低两位能被四整除为闰年（00年除外）当低两位为00时，高两位为400的整数倍为闰年，否则为平年。关于这个知识点具体请看：http://www.ruidan.com/mcu/2248.html
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity year is
port(m,cr:in std_logic;
mouth:in std_logic_vector(3 downto 0);
s1,s0 ,runout:out std_logic;
YH1,YH0,YL1,YL0:out std_logic_vector(3 downto 0));
end year;
architecture mm of year is
signal y11,y12,y01,y02:std_logic_vector(3 downto 0);
signal data1,data0 :std_logic_vector(6 downto 0);
signal run0,run1:std_logic_vector(2 downto 0);
signal c0,c1,c2,c3,r1,r0,r:std_logic;
begin
process(m,cr)
begin
--年低两位
if m'event and m='1' then
if y01=9 then y01<="0000";c0<='1';
else y01<=y01+1;c0<='0';
end if;
if data0=99 then data0<="0000000";
else data0<=data0+1;
end if;
if run0=3 then run0<="000";r0<='1';
else run0<=run0+1;r0<='0';
end if;
end if;
if c0'event and c0='1' then
if y02=9 then y02<="0000";c1<='1';
else y02<=y02+1;c1<='0';
end if;
end if;
--年高两位。
if c1'event and c1='1' then
if data1=99 then data1<="0000000";
else data1<=data1+1;
end if;
if run1=3 then run1<="000";
else run1<=run1+1;
end if;
if y11=9 then y11<="0000";c2<='1';
else y11<=y11+1;c2<='0';
end if;
end if;
if c2'event and c2='1' then
if y12=9 then y12<="0000";
else y12<=y12+1;
end if;
end if;
if run1/=0 and data0=0 then r1<='0';
else r1<='1';
end if;
r<=r0 and r1;
if mouth=2 then
if r='1' then s1<='1';s0<='1';
else s1<='1'; s0<='0';
end if;
elsif mouth=4 or mouth=6 or mouth=9 or mouth=11 then s1<='0';s0<='1';
else s1<='0';s0<='0';
end if;
end process;
YH1<=y12;YH0<=y11;YL1<=y02;YL0<=y01;runout<=r;
end;
二、月份的程序，公历。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mouth is
port(day,cr,tm:in std_logic;
m:out std_logic;
mouth1,mouth0,mouth:out std_logic_vector(3 downto 0));
end mouth;
architecture mm of mouth is
signal m1,m0,data:std_logic_vector(3 downto 0);
signal C,clk:std_logic;
signal ss:std_logic_vector(1 downto 0);
begin
process(day,cr,tm)
begin
clk<=day or (not tm);
if clk'event and clk='1' then
if data=12 then data<="0001";m<='1';
else data<=data+1;m<='0';
end if;
end if;
if data<=9 then m1<="0000";m0<=data;
elsif data=10 then m1<="0001";m0<="0000";
elsif data=11 then m1<="0001";m0<="0001";
elsif data=12 then m1<="0001";m0<="0010";
end if;
end process;
mouth1<=m1;mouth0<=m0; mouth<=data;
end;
三、日期，个月份的天数不相同，有2月28天（闰年29天），有30天有31天不等：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity day is
port(cp,cr,s0,s1:in std_logic;
day:out std_logic;
dayh,dayl:out std_logic_vector(3 downto 0));
end day;
architecture mm of day is
signal m1,m0:std_logic_vector(3 downto 0);
signal data:std_logic_vector(4 downto 0);
signal c:std_logic;
signal ss:std_logic_vector(1 downto 0);
begin
process(cp,cr)
variable CC:integer;
begin
ss<=s1 & s0;
case ss is
when"00"=>CC:=31;
when"01"=>CC:=30;
when"10"=>CC:=28;
when"11"=>CC:=29;
end case;
if cp'event and cp='1' then
if data=CC then data<="00001";m1<="0000";m0<="0001";c<='1';
else data<=data+1;m0<=m0+1;c<='0';
if m0=9 then m0<="0000";m1<=m1+1;
end if;
end if;
end if;
if cr='0' then m1<="0000";m0<="0001";data<="00001";
end if;
end process;
dayl<=m0;day<=c;dayh<=m1;
end;
四、时钟部分，一天24小时
library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity timer_day is
port(cr,min,hor,cp:in std_logic;
second,day,f500:out std_logic;
secL,secH,minL,minH,hourL,hourH:out std_logic_vector(3 downto 0));
end timer_day;
architecture dianzi of timer_day is
signal display,t0,t1,t2:std_logic_vector(8 downto 0);
signal c0,c1,c2,s0,s1,m0,m1,h0,h1,clk1,clk2,day0:std_logic;
signal sq0,sq1,mq0,mq1,hq0,hq1,xs:std_logic_vector(3 downto 0);
begin
process(cr,cp) --分频开始
begin
if cp'event and cp='1' then
if t0=499 then t0<="000000000";c0<='1';
else t0<=t0+1; c0<='0';
end if;
end if;
if c0'event and c0='1' then
if t1=199 then t1<="000000000";c1<='1';
else t1<=t1+1;c1<='0';
end if;
end if;
if c1'event and c1='1' then
if t2=199 then t2<="000000000";c2<='1';
else t2<=t2+1;c2<='0';
end if;
end if;
end process;
--分频结束 --秒计时开始
process(c2,cr,min)
begin
if c2'event and c2='1' then
if sq0=9 then sq0<="0000";s0<='1';
else sq0<=sq0+1;s0<='0';
end if;
end if;
if s0'event and s0='1' then
if sq1=5 then sq1<="0000"; s1<='1';
else sq1<=sq1+1;s1<='0';
end if;
end if;
if cr='0' then sq0<="0000";sq1<="0000";
end if;
if min='0' then sq0<="0000";sq1<="0000";
end if;
end process;--秒计时结束.
--分开始
process(s1,min)
begin
clk1<=s1 or (not min);--分调整按钮，按一下分加1同时将秒清0.
if clk1'event and clk1='1' then
if mq0=9 then mq0<="0000";m0<='1';
else mq0<=mq0+1; m0<='0';
end if;
end if;
if m0'event and m0='1' then
if mq1=5 then mq1<="0000";m1<='1';
else mq1<=mq1+1;m1<='0';
end if;
end if;
if cr='0' then mq1<="0000";mq0<="0000";
end if;--分结束
end process;
--小时开始
process(m1,hor)
begin
clk2<=m1 or (not hor);--时调整按钮，按一下小时加1.
if clk2'event and clk2='1' then day<=day0;
if hq0=9 then hq0<="0000";h0<='1';
else hq0<=hq0+1;h0<='0';
end if;
end if;
if h0'event and h0='1' then
if hq1=5 then hq1<="0000";h1<='1';
else hq1<=hq1+1;h1<='0';
end if;
end if;
if hq1=2 and hq0=3 then day0<='1';
else day0<='0';
end if;
if hq1=2 and hq0=4 then
hq0<="0000";hq1<="0000";
end if;
if cr='0' then hq0<="0000";hq1<="0000";
end if;--小时结束
end process;
secL<=sq0;secH<=sq1;minL<=mq0;minH<=mq1;hourL<=hq0;hourH<=hq1;
second<=c2;f500<=c0;
end ;
五、显示部分
显示部分如果显示的数量有限而显示的内容又较多，这时应给显示的内容分组，比如说万年历，可以把年月日分为一组，把时分秒分为一组，如果有天气情况可分为一组，这样先分组，再显示实现起来就比较清晰。
一）分组（分两组），八秒显示一组，实际中可视情况而定。
library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
entity xuan_dis is
port(sec