八选一数据选择器的VHDL程序

八选一须具选择器：用CASE语句。

LIBRARY E;
USE IEEE.D_LOGIC_1164.ALL;
EITY mux_8_1 IS
PORT (A,B,C,D,E,F,G,H,En:IN STD_LOGIC;
S:in STD_LOGIC_vector(2 downto 0);
Y: out STD_LOGIC);
end mux_8_1;
ARCHICTURE mux OF mux_8_1 IS
begin
process( S,A,B,C,D,E,F,G,H,En)
begin
if En='0' then
case S is
when "000" => Y<=A;
when "001" => Y<=B;
when "010" => Y<=C;
when "011" => Y<=D;
when "100" => Y<=E;
when "101" => Y<=F;
when "110" => Y<=G;
when "111" => Y<=H;
end case;
end if;
end process;
end mux;

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