VHDL语言之另一种编法74LS290

另一种编法LS290

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity LS290 is
port(R1,R0,S1,S0,clk:in std_logic;
Q:out std_logic_vector(3 downto 0);
Co:out std_logic);
end LS290;
architecture cccp of LS290 is
signal RR,SS:std_logic;
signal QI: std_logic_vector(3 downto 0);
signal C:std_logic;
begin
RR<=(R1 and R0) ;SS<=S1 and S0;
process(R1,R0,S1,S0,clk,RR,SS)
begin
if clk'event and clk='0' then
if QI<9 then QI<= QI+1;
else QI<="0000";
end if;
end if;
if RR='1' then QI<="0000";
end if;
if SS='1' then QI<="1001";
end if;
if QI=9 then C<='1';
else C<='0';
end if;
if clk'event and clk='0' then Co<=C;
end if;
Q<=QI;
end process;
end;

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