三段式状态机的vhdl程序

`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:24:52 03/24/2012
// Design Name:
// Module Name: jtd
// Project Name:
// Target s:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module jtd(clk,rst_n,key0,led0,led1
);
input clk,rst_n,key0;
output led0,led1;
reg clk1khz,clk1hz;
reg[1:0] state,next_state;
reg led0,led1;
reg[8:0] count2;
reg[14:0] count1;
reg[3:0] num;
parameter s1 = 2'b00, s2 = 2'b01, s3 = 2'b10, s4 = 2'b11;

//********1khz*******
always @(posedge clk or negedge rst_n)
begin
if(!rst_n) begin
count1 <= 0;
end
else if(count1 == 15'd25000) begin
clk1khz <= ~clk1khz;
count1 <= 0;
end
else begin
count1 <= count1+1;
end
end

//*******1hz**********
always @(posedge clk1khz or negedge rst_n)
begin
if(!rst_n) begin
count2 <= 0;
end
else if(count2 == 9'd500) begin
clk1hz = ~clk1hz;
count2 <= 0;
end
else begin
count2 <= count2 + 1;
end
end

always @(posedge clk1hz or negedge rst_n)
begin
if(!rst_n) begin
num <= 0;
end
else if(num == 4'd10) begin
num <= 0;
end
else begin
num <= num + 1;
end
end


//********状态机*******段一******
always @(posedge clk1hz or negedge rst_n)
begin
if(!rst_n)
state <= s1;
else
state <= next_state;
end

//******状态机******段二******
always @(state)
begin
if(!rst_n)
next_state = s1;
else
case(state)
s1:
if(key0 == 0)
next_state = s4;
else if(num == 4'd10)
next_state = s2;
else
next_state = s1;
s2:
if(key0==0)
next_state = s4;
else if(num == 4'd10)
next_state = s3;
else
next_state = s2;
s3:
if(key0 == 0)
next_state = s4;
else if(num == 4'd10)
next_state = s4;
else
next_state = s3;
s4:
if(key0 == 0)
next_state = s4;
else if(num == 4'd10)
next_state = s1;
else
next_state = s4;
default:
next_state = s1;
endcase
end

//******状态机******段三******
always @(posedge clk1hz or negedge rst_n)
begin
if(!rst_n) begin
led0 <= 0;
led1 <= 0;
end
else
case(state)
s1: begin
led0 <= 0;
led1 <= 0;
end
s2: begin
led0 <= 1;
led1 <= 0;
end
s3: begin
led0 <= 0;
led1 <= 1;
end
s4: begin
led0 <= 1;
led1 <= 1;
end
default: begin
led0 <= 0;
led1 <= 0;
end
endcase
end

endmodule

说明：00011011四个状态，复位时是00，不复位时，key0按下时是11，key0不按下时每10s进入下一个状态。
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