VHDL-AMS 常用程序模块
时间：2023-07-14 00:37:01
VHDL-AMS 是硬件描述语言VHDL（IEEE 1076-1993)的衍生部分。它包含了模拟和混合信号的扩展，以描述模拟和混合信号系统的行为。
基础模块
``` -------------------------------- -- 电阻 --------------------------------- LIBRARY IEEE; USE IEEE.electrical_systems.all; ENTITY resist IS GENERIC( R_value : real := 1000.0); PORT (TERMINAL tp,tm : electrical); END; ARCHITECTURE equ OF resist IS QUANTITY v ACROSS i THROUGH tp TO tm; BEGIN v == R_value*i; END; -------------------------------- -- 电容 --------------------------------- LIBRARY IEEE; USE IEEE.electrical_systems.all; ENTITY condensateur IS GENERIC( C_value : real := 1.0e-6); PORT (TERMINAL tp,tm : electrical); END; ARCHITECTURE equ OF condensateur IS QUANTITY v ACROSS i THROUGH tp TO tm; BEGIN i == C_value*v'dot; -- C_value*v == i'integ; END; -------------------------------- -- 直流电源 DC --------------------------------- LIBRARY IEEE; USE IEEE.electrical_systems.all; ENTITY V_dc IS GENERIC( DC_value : real := 10.0); PORT (TERMINAL tp,tm : electrical); END; ARCHITECTURE equ OF V_dc IS QUANTITY v ACROSS i THROUGH tp TO tm; BEGIN v == DC_value; END; -------------------------------- -- 交流电源 AC --------------------------------- LIBRARY IEEE; USE IEEE.electrical_systems.all; USE IEEE.math_real.all; ENTITY V_ac IS GENERIC( Vampl : real := 10.0;freq : real := 1.0e3; phase : real := 0.0); PORT (TERMINAL tp,tm : electrical); END; ARCHITECTURE equ OF V_ac IS QUANTITY v ACROSS i THROUGH tp TO tm; BEGIN v == Vampl*cos(math_2_pi*freq*NOW phase); END; ------------------------------------------------- -- testbench ------------------------------------------------- --LIBRARY IEEE; --USE IEEE.electrical_systems.all; --USE work.all;
--ENTITY test IS
--END;
--ARCHITECTURE equ OF test IS
-- TERMINAL ta,tb,tc : electrical;
--BEGIN
--
-- VCC : ENTITY V_dc(equ) GENERIC MAP (5.0) PORT MAP (ta, electrical_ref);
-- Ve : ENTITY V_ac(equ) GENERIC MAP (1.0) PORT MAP (ta, tb);
-- R1 : ENTITY resist(equ) PORT MAP (tb, tc);
-- C1 : ENTITY condensateur(equ) GENERIC MAP (1.0E-6) PORT MAP (tc, electrical_ref);
--END;
--------------------------------
-- 例子 ：限制器
---------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY limiteur IS
GENERIC( limp : real := 15.0;limm : real := 15.0);
PORT (TERMINAL te,ts : electrical);
END;
ARCHITECTURE behav OF limiteur IS
QUANTITY ve ACROSS te TO electrical_ref;
QUANTITY vs ACROSS io THROUGH ts ;
BEGIN
IF ve>limp USE
vs == limp;
ELSIF ve<-limm USE
vs == -limm;
ELSE
vs == ve;
END USE;
END;
-------------------------------------
-- 比较器
-------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY comparator IS
GENERIC( seuil : real := 2.5);
PORT (TERMINAL tp,ref : electrical;SIGNAL dout : OUT boolean);
END;
ARCHITECTURE ideal OF comparator IS
QUANTITY vin ACROSS tp TO ref;
BEGIN
dout<=vin'above(seuil);
END;
-------------------------------------
-- 简单的比较器
-------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY comparateur IS
GENERIC( level : real := 2.5);
PORT (TERMINAL ta : electrical;SIGNAL sd : OUT bit);
END;
ARCHITECTURE simple OF comparateur IS
QUANTITY vin ACROSS ta ;
BEGIN
PROCESS (vin'above(level))
BEGIN
IF vin'above(level) THEN
sd<='1';
ELSE
sd<='0';
END IF;
END PROCESS;
END;
ARCHITECTURE simple2 OF comparateur IS
QUANTITY vin ACROSS ta ;
BEGIN
sd<='1' WHEN vin'above(level)ELSE '0';
END;
----------------------------------
-- test bench
----------------------------------
--LIBRARY IEEE;
--USE IEEE.electrical_systems.all;
--USE work.all;
--ENTITY test IS
--END;
--ARCHITECTURE equ OF test IS
--TERMINAL ta : electrical;
--SIGNAL sd : bit ;
--BEGIN
--Ve : ENTITY V_ac(equ) GENERIC MAP (5.0,1000.0) PORT MAP (ta, electrical_ref);
--vcomp : ENTITY comparateur PORT MAP (ta,sd);
--
--END;
------------------------------------------------
-- 脉冲发生器
------------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY pulse_gen IS
GENERIC ( plow : real := 0.0;
phigh : real := 5.0;
trise : real := 1.0e-6;
tfall : real := 1.0e-6;
idelay : time := 1 ms;
pwidth : time := 5 ms) ;
PORT (TERMINAL t : electrical);
END;
ARCHITECTURE bhv OF pulse_gen IS
QUANTITY vout ACROSS iout THROUGH t;
SIGNAL spulse : real := PLOW;
BEGIN
PROCESS BEGIN
WAIT FOR idelay;
LOOP
spulse <= PHIGH;
WAIT FOR PWIDTH;
spulse <= PLOW;
WAIT FOR PWIDTH;
END LOOP;
END PROCESS;
vout == spulse;
BREAK ON spulse;
END;
ARCHITECTURE bhv2 OF pulse_gen IS
QUANTITY vout ACROSS iout THROUGH t;
SIGNAL spulse : real := PLOW;
BEGIN
PROCESS BEGIN
WAIT FOR idelay;
LOOP
spulse <= PHIGH;
WAIT FOR PWIDTH;
spulse <= PLOW;
WAIT FOR PWIDTH;
END LOOP;
END PROCESS;
vout == spulse'ramp(trise,tfall);
END;
-------------------------------------------
-- 有初始化的电容器
-------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY capacitor IS
GENERIC( C_value : real := 1.0e-6;V0 : real := real'low);
PORT (TERMINAL tp,tm : electrical);
END;
ARCHITECTURE equ OF capacitor IS
QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
i == C_value*v'dot;
BREAK v=>V0 WHEN V0/=real'low;
-- C_value*v == i'integ;
END;
ARCHITECTURE equ2 OF capacitor IS
QUANTITY v ACROSS i THROUGH tp TO tm;
QUANTITY q : charge;
BEGIN
q == C_value*v;
i == q'dot;
BREAK FOR q USE v=>V0 WHEN V0/=real'low;
-- C_value*v == i'integ;
END;
----------------------------------------------
-- 双初始条件电容
----------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY capacitor2 IS
GENERIC( C_value : real := 1.0e-6; V0 : real := real'low);
PORT (TERMINAL tp,tm : electrical);
END;
ARCHITECTURE equ OF capacitor2 IS
QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN USE
v==V0;
ELSE
i == C_value*v'dot;
END USE;
END;
--------------------------------
-- 交流电源 AC
---------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE IEEE.math_real.all;
ENTITY V_ac IS
GENERIC( Vampl : real := 10.0;freq : real := 1.0e3; phase : real := 0.0);
PORT (TERMINAL tp,tm : electrical);
END;
ARCHITECTURE equ OF V_ac IS
CONSTANT ac_mag : real := 1.0;
CONSTANT ac_phase : real := 0.0;
QUANTITY ac_spec : real SPECTRUM ac_mag, ac_phase;
QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
IF DOMAIN = FREQUENCY_DOMAIN USE
v == ac_spec;
ELSE
v == Vampl*cos(math_2_pi*freq*NOW+phase);
END USE;
END;
ARCHITECTURE equ2 OF V_ac IS
CONSTANT ac_mag : real := 1.0;
CONSTANT ac_phase : real := 0.0;
QUANTITY ac_spec : real SPECTRUM ac_mag, ac_phase;
QUANTITY v ACROSS i THROUGH tp TO tm;
BEGIN
v == Vampl*cos(math_2_pi*freq*NOW+phase)+ac_spec;
END;
------------------------------------------------
-- test bench (带通)
------------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE work.all;
ENTITY test IS
END;
ARCHITECTURE equ OF test IS
TERMINAL tb, tc : electrical;
BEGIN
VAC : ENTITY V_ac PORT MAP (tb, electrical_ref);
R1 : ENTITY Resist(equ) PORT MAP (tb, tc);
RLC1 : ENTITY RLCp GENERIC MAP (1.0e3,25.0e-3,1.0e-6) PORT MAP (tc, electrical_ref);
end;
-------------------------------------------
--有热噪声性质的电阻
-------------------------------------------
--amb_temp est une variable partag閑
--{library clause}
LIBRARY IEEE;
USE IEEE.electrical_systems.ALL;
ENTITY R_noise IS
GENERIC (R_value : real := 1000.0);
PORT (TERMINAL vp, vm : electrical);
END;
ARCHITECTURE equ OF R_noise IS
QUANTITY V ACROSS I THROUGH vp TO vm;
CONSTANT amb_temp : real := 300.0;
CONSTANT K : real := 1.0;
QUANTITY noise_src : real NOISE 4.0*amb_temp*K/R_value;
BEGIN
V==R_value*I+noise_src;
END;
----------------------------------------------
-- RC 滤波
----------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
ENTITY filtreRC_pb IS
GENERIC (Rv : real := 1.0e3; Cv : real := 1.0e-6);
PORT (TERMINAL tin, tout : electrical);
END;
ARCHITECTURE simple OF filtreRC_pb IS
QUANTITY vin ACROSS iin THROUGH tin;
QUANTITY vout ACROSS iout THROUGH tout;
BEGIN
vin-vout==Rv*Cv*vout'dot;
iin == 0.0;
END;
ARCHITECTURE laplace OF filtreRC_pb IS
QUANTITY vin ACROSS iin THROUGH tin;
QUANTITY vout ACROSS iout THROUGH tout;
CONSTANT num : real_vector := (1.0,0.0);
CONSTANT den : real_vector := (1.0, Rv*Cv);
BEGIN
vout==vin'ltf(num,den);
iin == 0.0;
END;
----------------------------------------
-- test bench RC 滤波
----------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.all;
USE work.all;
ENTITY test IS END;
ARCHITECTURE equ OF test IS
TERMINAL te,ts : electrical;
BEGIN
VAC : ENTITY V_AC PORT MAP (te, electrical_ref);
filtre : ENTITY filtreRC_pb(laplace) PORT MAP (te,ts);
END;
--------------------------------
-- 二极管
--------------------------------
LIBRARY IEEE;
USE ieee.electrical_systems.all;
USE ieee.fundamental_constants.all;
USE Ieee.math_real.all;
ENTITY diode IS
GENERIC (Iss : real := 1.0e-14; n : real := 1.0; vj : real := 0.8;tt, cj0,rs : real :=0.0;
temperature : real := 300.0);
PORT (TERMINAL anode, cathode : electrical);
END;
ARCHITECTURE phys1 OF diode IS
QUANTITY vd ACROSS id,ic THROUGH anode TO cathode;
QUANTITY qc : charge;
CONSTANT vt : real := phys_k*temperature/PHYS_Q;
BEGIN
ic == qc'dot;
qc == tt*id-2.0*cj0*(vj**2-vj*vd)**0.5;
id == iss*(exp((vd-rs*id)/(n*vt))-1.0);
END;
ARCHITECTURE phys2 OF diode IS
TERMINAL ti : electrical;
QUANTITY vd ACROSS id,ic THROUGH ti TO cathode;
QUANTITY qc : charge;
CONSTANT vt : real := phys_k*temperature/PHYS_Q;
BEGIN
ri : entity work.resistance generic map (rs) port map (anode , ti);
ic == qc'dot;
qc == tt*id-2.0*cj0*(vj**2-vj*vd)**0.5;
id == iss*(exp(vd/(n*vt))-1.0);
END;
--ARCHITECTURE ideal OF diode IS
--CONSTANT VT0 : real := 0.65;
--CONSTANT ra : real := 10.0;
--QUANTITY vd ACROSS id THROUGH anode TO cathode;
--BEGIN
--IF vd
--id == 0.0;
--ELSE
--vd == VT0+ra*id;
--END USE;
--END;
-------------------------------------------
-- 有热噪声的二极管
-------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.ALL;
USE IEEE.thermal_systems.ALL;
USE IEEE.fundamental_constants.ALL;
USE ieee.math_real.ALL;
ENTITY diodth IS
GENERIC (Iss : real := 1.0e-12; n : real := 1.0; tt, cjo, vj, rs : real := 0.0) ;
PORT (TERMINAL anode , cathode : electrical; TERMINAL junction : thermal );
END;
ARCHITECTURE level0 OF diodth IS
QUANTITY vd ACROSS id,ic THROUGH anode TO cathode;
QUANTITY temp ACROSS power THROUGH junction TO thermal_ref ;
QUANTITY qc : charge;
QUANTITY vt : voltage; -- electromagneticforce=tension
BEGIN
ic ==qc'dot;
qc ==tt*id-2.0*cjo*(vj**2-vj*vd)**0.5;
id == iss*(exp((vd-rs*id)/(n*vt))-1.0);
vt==temp*phys_K/phys_Q;
power==-vd*id;
END ARCHITECTURE level0;
----------------------------------------
-- 热敏电阻
----------------------------------------
LIBRARY IEEE;
USE IEEE.thermal_systems.ALL;
ENTITY Resistanceth IS
GENERIC (R_thermique : real := 100.0) ;
PORT (TERMINAL tpth,tmth : thermal );
END;
ARCHITECTURE level0 OF Resistanceth IS
QUANTITY temp ACROSS power THROUGH tpth TO tmth;
BEGIN
temp ==R_thermique*power;
END ARCHITECTURE level0;
----------------------------------------
-- 热敏电容
----------------------------------------
LIBRARY IEEE;
USE IEEE.thermal_systems.ALL;
ENTITY capath IS
GENERIC (C_thermique : real := 1.0e-3;T_amb : real :=300.0) ;
PORT (TERMINAL tpth,tmth : thermal );
END;
ARCHITECTURE level0 OF capath IS
QUANTITY temp ACROSS power THROUGH tpth TO tmth;
BEGIN
BREAK temp=>T_amb;
power ==C_thermique*temp'dot;
END ARCHITECTURE level0;
---------------------------------------
-- 热源
---------------------------------------
LIBRARY IEEE;
USE IEEE.thermal_systems.ALL;
ENTITY sourceth IS
GENERIC (C_thermique : real := 1.0e-3) ;
PORT (TERMINAL tpth,tmth : thermal );
END;
ARCHITECTURE level0 OF sourceth IS
QUANTITY temp ACROSS power THROUGH tpth TO tmth;
CONSTANT T_amb : real := 300.0;
BEGIN
power ==T_amb/100.0;
END ARCHITECTURE level0;
------------------------------------------
-- 热测试
------------------------------------------
LIBRARY IEEE;
USE IEEE.electrical_systems.ALL;
USE IEEE.thermal_systems.ALL;
USE work.ALL;
ENTITY test IS END;
ARCHITECTURE test_a OF test IS
TERMINAL anode : electrical;
TERMINAL junction : thermal;
BEGIN
VDD : ENTITY V_dc generic map (0.6) PORT MAP (anode,electrical_ref);
D1 : entity diodth port map (anode,electrical_ref,junction);
Rth1: ENTITY Resistanceth port map (junction, thermal_ref);
Cth1 : ENTITY Capath port map (junction, thermal_ref);
sth1 : ENTITY sourceth port map (thermal_ref,junction);
END;
------------------------------------------------
-- CTP热敏电阻
------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
ENTITY CTP IS
GENERIC (R_value_zero_degre_C : real := 1000.0; R_coeff : real := 1.0);
PORT (TERMINAL tp,tm : electrical; QUANTITY temp : IN real);
END;
ARCHITECTURE simple Of CTP IS
QUANTITY V ACROSS I THROUGH tp TO tm;
BEGIN
V==R_value_zero_degre_C*(1.0+R_coeff*temp)*I;
END;
--------------------------------------------
-- 热源
--------------------------------------------
library ieee;
use ieee.electrical_systems.all;
ENTITY sourceT IS
PORT ( QUANTITY temp : OUT real);
END;
ARCHITECTURE simple Of sourceT IS
BEGIN
temp == now;
END;----------------------------------------------
---------------------------------------
-- NMOS
---------------------------------------
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.MATH_REAL;
ENTITY NMOS IS
GENERIC (Vt : REAL := 0.55; beta : real := 70.0e-6);
PORT ( TERMINAL drain, gate, source, bulk : ELECTRICAL);
END ENTITY NMOS;
-- architecture
ARCHITECTURE a_NMOS OF NMOS IS
CONSTANT RN : real := 1.0e9;
QUANTITY VDS ACROSS IDS,IRN THROUGH drain TO source;
QUANTITY VGS ACROSS gate TO source;
QUANTITY Vbss ACROSS bulk TO source;
BEGIN
IF VGSUSE
Ids==0.0;
ELSE
IF VDSUSE
IDS==beta*((VGS-VT)*VDS-(VDS**2.0)/2.0);
ELSE
IDS==beta*((VGS-VT)**2.0)/2.0;
END USE;
END USE;
VDS == RN*IRN;
END ARCHITECTURE a_NMOS;
---------------------------------------
-- PMOS
---------------------------------------
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.MATH_REAL;
ENTITY PMOS IS
GENERIC (Vt : REAL := -0.55; beta : real := 70.0e-6);
PORT ( TERMINAL drain, gate, source, bulk : ELECTRICAL);
END ENTITY PMOS;
-- architecture
ARCHITECTURE a_PMOS OF PMOS IS
CONSTANT RP : real := 1.0e9;
QUANTITY VDS ACROSS IDS,IRP THROUGH drain TO source;
QUANTITY VGS ACROSS gate TO source;
QUANTITY Vbss ACROSS bulk TO source;
BEGIN
IF VGS>VT USE
Ids==0.0;
ELSE
IF VDS>(VGS-VT) USE
IDS==-beta*((VGS-VT)*VDS-(VDS**2.0)/2.0);
ELSE
IDS==-beta*((VGS-VT)**2.0)/2.0;
END USE;
END USE;
VDS == RP*IRP;
END ARCHITECTURE a_PMOS;
------------------------------------------------
-- rampe
------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
entity V_rampe is
generic ( Vmin : real :=0.0;
pente : real := 1.0) ;
port (terminal tp,tm : electrical);
end entity V_rampe;
architecture behav of V_rampe is
quantity v across i through tp to tm;
begin
v==Vmin+pente*NOW;
end;
---------------------------------------
-- CMOS
---------------------------------------
LIBRARY IEEE;
USE IEEE.ELECTRICAL_SYSTEMS.ALL;
USE IEEE.MATH_REAL;
ENTITY CMOS IS
GENERIC (mtype: real := 1.0;Vt : REAL := 0.55; beta : real := 70.0e-6);
PORT ( TERMINAL drain, gate, source, bulk : ELECTRICAL);
END ENTITY CMOS;
-- architecture
ARCHITECTURE a_CMOS OF CMOS IS
CONSTANT RDS : real := 1.0e9;
QUANTITY VDS ACROSS IDS,IRDS THROUGH drain TO source;
QUANTITY VGS ACROSS gate TO source;
QUANTITY Vbss ACROSS bulk TO source;
BEGIN
IF mtype*VGSUSE
Ids==0.0;
ELSE
IF mtype*VDSUSE
IDS==mtype*beta*((VGS-VT)*VDS-(VDS**2.0)/2.0);
ELSE
IDS==mtype*beta*((VGS-VT)**2.0)/2.0;
END USE;
END USE;
VDS == RDS*IRDS;
END ARCHITECTURE a_CMOS;
------------------------------------------------------
-- NMOS 和 PMOS 特性
------------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;
entity caracteristique_CMOS IS end;
ARCHITECTURE Test OF caracteristique_CMOS IS
TERMINAL tdd, td,tgn,tgp : electrical;
BEGIN
VGN : entity V_dc GENERIC MAP (2.0) PORT MAP (tgn,electrical_ref);
-- NMOS1 : entity NMOS PORT MAP (tdd,tgn,electrical_ref,electrical_ref);
NMOS1 : entity CMOS PORT MAP (tdd,tgn,electrical_ref,electrical_ref);
VGP : entity V_dc GENERIC MAP (3.0) PORT MAP (tgp,electrical_ref);
VDD : entity V_dc GENERIC MAP (5.0) PORT MAP (td,electrical_ref);
-- PMOS1 : entity PMOS PORT MAP (tdd,tgp,td,td);
PMOS1 : entity CMOS GENERIC MAP (-1.0,-0.55) PORT MAP (tdd,tgp,td,td);
VDS : entity V_rampe GENERIC MAP(0.0,1.0) PORT MAP (tdd,electrical_ref);
END ;
--------------------------------------------------
---- CMOS 反相器
--------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;
entity inverseur_CMOS IS end;
ARCHITECTURE Test OF inverseur_CMOS IS
TERMINAL tdd, te,ts : electrical;
BEGIN
VDD : entity V_dc GENERIC MAP (5.0) PORT MAP (tdd,electrical_ref);
-- PMOS1 : entity PMOS PORT MAP (ts,te,tdd,tdd);
PMOS1 : entity CMOS GENERIC MAP (-1.0,-0.55) PORT MAP (ts,te,tdd,tdd);
-- NMOS1 : entity NMOS PORT MAP (ts,te,electrical_ref,electrical_ref);
NMOS1 : entity CMOS GENERIC MAP (1.0,0.55) PORT MAP (ts,te,electrical_ref,electrical_ref);
VGG : entity V_rampe GENERIC MAP(0.0,1.0) PORT MAP (te,electrical_ref);
END;
-----------------------------------------------------
-- 静态/动态 MOS
-----------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
use ieee.fundamental_constants.all;
----------------------------------
---------- ENTITIE ----------
----------------------------------
entity mos is
generic( Vt0 : real := 0.85;----Volt
Weff: real :=0.8;----um
Leff: real :=0.55 ;----um
Kp : real := 120.0;----uA/V**2
gamma : real :=0.7;----V**0.5
ni : real :=1.45e-2;----um**-3
Nsub : real :=52.0e3;----um**-3
lam: real:=0.001; ----V**-1
T : real := 300.0); ----K
port ( terminal drain, gate, source, bulk : electrical);
end mos;
--------------------------------------------------
-------- ARCHITECTURE
--------------------------------------------------
architecture mos1 of mos is
--------------------
function draincourant(constant Vgs, Vds, Vbs :real ) return real is
variable vt, phi, vth, vdsat, result :real;
begin
Vt:=phys_K*T/phys_q;
Phi := 2.0*Vt*log( Nsub/ni);
if Vbs<=0.0 then
vth := Vt0-gamma*sqrt(phi)+gamma*sqrt(Phi-Vbs);
else
vth :=Vt0-gamma*0.5*Vbs/sqrt(phi);
end if;
vdsat :=vgs-vth;
if vgs < vth then
result:=0.0;
else if Vds < (Vgs -Vth) then
result := (Kp*Weff/Leff)*Vds*(Vgs-Vth-Vds/2.0)*(1.0+lam*vds);
else
result :=((Kp*Weff)/(2.0*Leff))*((Vgs - Vth)**2.0)*(1.0+lam*vds);
end if;
end if;
return result;
end function;
--- -----
quantity Id through drain to source;
quantity Vbs across bulk to source;
quantity Vds across drain to source;
quantity Vgs across gate to source;
begin
Id == draincourant(Vgs, Vds, Vbs)*1.0e-6;
end architecture mos1;
----------------------------
----capacites du mos---
----------------------------
library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
use ieee.fundamental_constants.all;
----------------------------------
---------- ENTITIE ----------
----------------------------------
entity moscap is
generic( Vt0 : real := 0.85;
Weff: real :=0.8;
Leff: real :=0.55 ;
cox: real :=2.75e-15;
Kp : real := 120.0;
gamma : real :=0.7;
ni : real :=1.45e-2;
Nsub : real :=52.0e3;
lam: real:=0.001;
T : real := 300.0);
port ( terminal drain1, gate1, source1, bulk1: electrical);
end moscap;
--------------------------------------------------
-------- ARCHITECTURE
--------------------------------------------------
architecture mos1 of moscap is
-----------------
function threshold(constant Vgs, Vds, Vbs, vt, phi:real ) return real is
variable result :real;
begin
if Vbs<=0.0 then
result := Vt0-gamma*sqrt(phi)+gamma*sqrt(Phi-Vbs);
else
result :=Vt0-gamma*0.5*Vbs/sqrt(phi);
end if;
return result;
end function;
constant capox: real :=cox*weff*leff;
constant Vt: real :=phys_K*T/phys_q;
constant Phi: real:= 2.0*Vt*log( Nsub/ni);
quantity vth:real;
quantity vdsat:real;
quantity Vbs across bulk1 to source1;
quantity Vds across drain1 to source1;
quantity Vdb across drain1 to bulk1;
quantity Vgs across igs through gate1 to source1;
quantity Vgd across igd through gate1 to drain1;
quantity Vgb across igb through gate1 to bulk1;
quantity Cgb:real;
quantity Cgd:real;
quantity Cgs:real;
begin
vth == threshold(vgs, Vds, Vbs, vt, phi);
vdsat==vgs-vth;
if (vgs-vth)<=-phi use
Cgb==capox;
Cgd==0.0;
Cgs==0.0;
else if (vgs-vth)<=-phi/2.0 and (vgs-vth)>-phi use
Cgb==-capox*(vgs-vth)/phi;
Cgd==0.0;
Cgs==0.0;
else if (vgs-vth)<0.0 and (vgs-vth)>-phi/2.0 use
Cgb==-capox*(vgs-vth)/phi;
Cgd==0.0;
Cgs==(capox/1.5)*(2.0*(vgs-vth)/phi+1.0);
else
if vdsuse
Cgb==0.0;
Cgd==(capox/1.5)*(1.0-((vdsat-vbs)/(2.0*(vdsat-vbs)-vdb))**2.0);
Cgs==(capox/1.5)*(1.0-((vdsat-vds)/(2.0*(vdsat-vbs)-vdb))**2.0);
else
Cgb==0.0;
Cgd==0.0;
Cgs==capox/1.5;
end use;
end use;
end use;
end use;
igs == Cgs * Vgs'dot;
igd == Cgd * Vgd'dot;
igb == Cgb * Vgb'dot;
end architecture mos1;
---------------------------------
library ieee;
use ieee.electrical_systems.all;
use ieee.math_real.all;
use ieee.fundamental_constants.all;
entity mos3 is
port (terminal gg,dd,ss,bb: electrical);
end entity mos3;
architecture structural of mos3 is
begin
tranmos: entity work.mos(mos1)
port map ( gate=>gg ,drain=> dd, source=> ss, bulk=>bb );
capa: entity work.moscap(mos1)
port map ( gate1=>gg , drain1=> dd, source1=> ss, bulk1=>bb );
end architecture structural;
------------------------------------------------------
------------------------------------------------------
-- 动态NMOS特性
------------------------------------------------------
library ieee;
use ieee.electrical_systems.all;
use work.all;
entity caracteristique_MOS IS end;
ARCHITECTURE Test OF caracteristique_MOS IS
TERMINAL tdd, td,tgn,tgp : electrical;
BEGIN
VGN : entity V_dc GENERIC MAP (2.0) PORT MAP (tgn,electrical_ref);
NMOS1 : entity M 
