FDC636P
数据手册.pdfP沟道逻辑电平增强模式场效应晶体管 P-Channel Logic Level Enhancement Mode Field Effect Transistor
P-Channel Logic Level Enhancement Mode Field Effect Transistor General Description These P-Channel logic level enhancement mode power field effect transistors are produced using "s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features SuperSOT TM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDSON. Exceptional on-resistance and maximum DC current capability.