DS90UR906QSQE/NOPB

TEXAS INSTRUMENTS  DS90UR906QSQE/NOPB  SerDes, 解串器, 1.82 Gbps, LVDS, LVCMOS, WQFN, 60 引脚

The is a FPD-Link II Deserializer Chipset translates a parallel RGB video interface into a high-speed serialized interface over a single pair. This serial bus scheme makes system design easy by eliminating skew problems between clock and data, reducing the number of connector pins, reducing the interconnect size, weight and easing overall PCB layout. In addition, internal DC-balanced decoding is used to support AC-coupled interconnects. The deserializer recovers the data RGB and control signals and extracts the clock from the serial stream. It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status LOCK output signal is provided. Serial transmission is optimized by user-selectable de-emphasis, differential output level select features and receiver equalization.

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AC-coupled STP interconnect cable up to 10m

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Integrated termination

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At speed link BIST mode and reporting pin

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RGB888 + VS, HS, DE support

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Power down mode minimizes power dissipation

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Backward compatible mode for operation with older generation devices

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Fast random data lock

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No reference clock required

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Adjustable input receiver equalization

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Lock real time link status reporting pin

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EMI minimization on output parallel bus SSCG

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Output slew control OS

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5 to 65MHz PCLK support 140Mbps to 1.82Gbps

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1.8 or 3.3V Compatible LVCMOS I/O interface

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>8kV HBM and ISO 10605 ESD rating

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Green product and no Sb/Br