DS90LV110ATMT

TEXAS INSTRUMENTS  DS90LV110ATMT  驱动器, LVDS, 数据/时钟分配器, LVDS, 145 ps, 160 mA, -40 °C, 85 °C, 3 V

The is a 1 to 10 Data/Clock Distributor utilizing LVDS low voltage differential signalling technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution/fan-out replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. It accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin.

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Balanced output impedance

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LVDS input failsafe

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Receiver open, shorted and terminated input failsafe

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Output channel-to-channel skew is 35ps typical

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Differential output voltage VOD is 320mV typical with 100R termination load

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LVDS receiver inputs accept LVPECL signals

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Fast propagation delay 2.8ns typical