DM385AAAR21

DM385和DM388 DaVincia ？ ¢数字媒体处理器 DM385 and DM388 DaVinci™ Digital Media Processor

* High-Performance DaVinci Digital Media Processors * Up to1000-MHzARM® Cortex™-A8 RISC Processor * Up to2000ARM Cortex-A8 MIPS * ARM Cortex-A8 Core * ARMv7 Architecture * In-Order, Dual-Issue, Superscalar Processor Core * NEON™ Multimedia Architecture * Supports Integer and Floating Point * Jazelle® RCT Execution Environment * ARM Cortex-A8 Memory Architecture * 32KB of Instruction and Data Caches * 256KB of L2 Cache with ECC * 64KB of RAM, 48KB of Boot ROM * 256KB of On-Chip Memory Controller OCMC RAM * Imaging Subsystem ISS * Face Detect FD Engine * Hardware Face Detection for up to 35 Faces Per Frame * Programmable High-Definition Video Image Coprocessing HDVICP v2Engine * Encode, Decode, Transcode Operations * H.264 BP/MP/HP, MPEG-2, VC-1, MPEG-4 SP/ASP, JPEG/MJPEG * Fourth-Generation Motion-Compensated Noise Filter DM388 Only * Media Controller * Controls the HDVPSS, HDVICP2, and ISS * Endianness * ARM Instructions and Data – Little Endian * HD Video Processing Subsystem HDVPSS * 32-Bit DDR2, DDR3, and DDR3L SDRAM Interface * General-Purpose Memory Controller GPMC * Enhanced Direct Memory Access EDMA Controller * Four Transfer Controllers * 64 Independent DMA Channels * 8 QDMA Channels * Ethernet Switch with Dual 10-, 100-, or 1000-Mbps External Interfaces EMAC Software * IEEE 802.3 Compliant 3.3-V I/O Only * MII/RMII/GMII/RGMII Media Independent Interfaces * Management Data I/O MDIO Module * Reset Isolation * IEEE 1588 Time-Stamping and Industrial Ethernet Protocols * Dual USB 2.0 Ports with Integrated PHYs * USB2.0 High- and Full-Speed Clients * USB2.0 High-, Full-, and Low-Speed Hosts * Supports End Points 0-15 * One PCI Express 2.0 Port with Integrated PHY * Eight 32-Bit General-Purpose Timers Timer1–8 * One System Watchdog Timer WDT0 * Three Configurable UART/IrDA/CIR Modules * UART0 with Modem Control Signals * Supports up to 3.6864 Mbps * SIR, MIR, FIR 4.0 MBAUD, and CIR * Four Serial Peripheral Interfaces SPIs up to48 MHz * Each with Four Chip Selects * ThreeMMC/SD/SDIO Serial Interfaces up to 48 MHz * Supporting up to 1-, 4-, or 8-Bit Modes * Four Inter-Integrated Circuit I2C Bus™Ports * Two Multichannel Audio Serial Ports McASP * Six Serializer Transmit and Receive Ports * Two Serializer Transmit and Receive Ports * DIT-Capable For S/PDIF All Ports * Four Audio Tracking Logic ATL Modules * Real-Time Clock RTC * One-Time or Periodic Interrupt Generation * Up to 125 General-Purpose I/O GPIO Pins * One Spin Lock Module with up to 128 Hardware Semaphores * One Mailbox Module with 12 Mailboxes * On-Chip ARM ROM Bootloader RBL * Power, Reset, and Clock Management * SmartReflex™ Technology Level 2b * Multiple Independent Core Power Domains * Multiple Independent Core Voltage Domains * Support for Multiple Operating Points per Voltage Domain * Clock Enable and Disable Control for Subsystems and Peripherals * 32KB of Embedded Trace Buffer™ ETB™ and 5-pin Trace Interface forDebug * IEEE 1149.1 JTAG Compatible * 609-Pin Pb-Free BGA Package AAR Suffix, 0.8-mm Effective Pitch with Via ChannelTechnology to Reduce PCB Cost 0.5-mm Ball Spacing * 45-nm CMOS Technology * 1.8- and 3.3-V Dual Voltage Buffers for General I/O