CD4059AE

TEXAS INSTRUMENTS  CD4059AE  逻辑芯片, 除以N计数器, 24DIP

The is a CMOS programmable Divide-by-N Counter that can be programmed to divide an input frequency by any number "N" from 3 to 15,999. The output signal is a pulse one clock-cycle wide occurring at a rate equal to the input frequency divided-by-N. This single output has TTL drive capability. The down-counter is preset by means of 16 jam inputs. The three Mode-Select Inputs Ka, Kb and Kc determine the modulus divide-by number of the first and last counting sections in accordance with the truth table. Every time the first fastest counting section goes through one cycle, it reduces by 1 the number that has been preset jammed into the three decades of the intermediate counting section and into the last counting section, which consists of flip-flops that are not needed for operating the first counting section. The intermediate counting section consists of three cascaded BCD decade 10 counters presettable by means of Jam Inputs J5 through J16.

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Fully static operation

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Master preset initialization

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Latchable ÷N output

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Quiescent current specified to 15V

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Green product and no Sb/Br