CDC111FN

1号线到9线差分LVPECL时钟驱动器 1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER

The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs CLKIN, CLKIN\\\\ to nine pairs of differential clock Y, Y\\\\ outputs with minimum skew for clock distribution. It is specifically designed for driving 50- transmission lines.

When the output-enable OE\\\\ is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states Y outputs are in the low state, Y\ outputs are in the high state.

The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.

The CDC111 is characterized for operation from 0°C to 70°C. View datasheet View product folder