74LVCHR32245AZKER

具有三态输出的32位总线收发器 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

This 32-bit quad-octal noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCHR32245A is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.

This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control DIR input. The output-enable OE\ input can be used to disable the device so that the buses are effectively isolated.

The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of this device for down translation in a mixed-voltage environment.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input circuit and is not disabled by OE\ or DIR.