MC100EP809FAR2G

3.3V 1 ： 9差分HSTL / PECL到HSTL时钟驱动器与LVTTL时钟选择和启用 3.3V 1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable

The MC100EP809 is a low skew 2:1:9 differential bus clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are one differential HSTL and one differential LVPECL. Both input pairs can accept LVDS levels. They are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable OE, which is LVTTL, is synchronous so that the outputs will only be enabled/disabled when they are already in LOW state.The MC100EP809 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration. To ensure that tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open unterminated without affecting skew.Designers can take advantage of the EP809"s performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single-end by biasing the non-driven pin in an input pair.

Features

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100 ps Typical Device-to-Device Skew

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15 ps Typical Within Device Skew

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HSTL Compatible Outputs Drive 50Ω to Ground with no Offset Voltage

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Maximum Frequency > 750 MHz

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850 ps Typical Propagation Delay

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Fully Compatible with Micrel SY89809L

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PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V

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Open Input Default State

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Pb-Free Packages are Available