SN74LV74AQDRQ1

双上升沿触发的D型触发器 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

description/ordering informationS

This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation.

A low level at the preset PRE or clear CLR inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive high, data at the data D inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

Qualified for Automotive Applications

2-V to 5.5-V VCC Operation

Max tpd of 13 ns at 5 V

Typical VOLP Output Ground Bounce

  <0.8 V at VCC = 3.3 V, TA = 25°C

Typical VOHV Output VOH Undershoot

  >2.3 V at VCC = 3.3 V, TA = 25°C

Support Mixed-Mode Voltage Operation on All Ports

Ioff Supports Partial-Power-Down Mode Operation

Latch-Up Performance Exceeds 250 mA Per JESD 17

ESD Protection Exceeds JESD 22

  − 2000-V Human-Body Model A114-A

  − 200-V Machine Model A115-A

  − 1000-V Charged-Device Model C101