SN65LVDM050D

高速差分线路驱动器和接收 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS

The is a differential Line Driver and Receiver uses low-voltage differential signaling LVDS to achieve high signaling rates. This circuit is similar to A/EIA-644 standard compliant devices SN65LVDS counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247mV across a 50R load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receiver detects a voltage difference of 50mV with up to 1V of ground potential difference between a transmitter and receiver. The intended application of this device and signaling technique is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100R characteristic impedance. The transmission media may be printed-circuit board traces, backplanes or cables.

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Typical full-duplex signalling rate of 100Mbps

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Bus-terminal ESD exceeds 12kV

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Low-voltage differential signaling with typical output voltage of 340mV with a 50R load

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Valid output with as little as 50mV input voltage difference

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Propagation delay time - 1.7ns Typical driver and 3.7ns typical receiver

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Power dissipation at 200MHz - 50mW Typical driver and 60mW typical receiver

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LVTTL input levels are 5V tolerant

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Driver is high-impedance when disabled or with VCC <1.5V

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Receiver has open-circuit failsafe design

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Green product and no Sb/Br