SN65LVDM180D

TEXAS INSTRUMENTS  SN65LVDM180D  芯片, 收发器, LVDS, 150MBPS, SOIC-14

逻辑类型Logic Type| \---|--- 电路数Number of Circuits| 收发器 输入数Number of Inputs| 电源电压VccVoltage - Supply| 静态电流IqCurrent - Quiescent Max| 输出高，低电平电流Current - Output High, Low| 79MHz 低逻辑电平Logic Level - Low| 2.7nS 高逻辑电平Logic Level - High| 正边沿 传播延迟时间@Vcc，CLMax Propagation Delay @ V, Max CL| 20µA,10µA Description & Applications| 3 V ~ 3.6 V 描述与应用| HIGH-SPEED DIFFERENAL LINE DRIVERS AND RECEIVERS description The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling LVDS to achieve signaling rates as high as 400 Mbps. These circuits are similar to TIA/EIA-644 standard compliant devices SN65LVDS counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV into a 50-Ω load and allows double-terminated lines and half-duplex operation. The receivers detect a voltage difference of 100 mV with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of these devices and signaling technique is half-duplex or multiplex baseband data transmission over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media may be printed-circuit board traces, backplanes, or cables. Low-Voltage Differential Drivers and Receivers for Half-Duplex Operation Signaling Rates up to 400 Mbps Bus-Terminal ESD Exceeds 12 kV Operates from a Single 3.3 V Supply Low-Voltage Differential Signaling with Typical Output Voltages of 340 mV with a 50-Ω Load Propagation Delay Times Driver: 1.7 ns Typ Receiver: 3.7 ns Typ Power Dissipation at 200 MHz Driver: 50 mW Typical Receiver: 60 mW Typical LVTTL Input Levels are 5 V Tolerant Driver is High Impedance When Disabled or With VCC < 1.5 V Receiver has Open-Circuit Fail Safe Surface-Mount Packaging D Package SOIC DGK Package MSOP ’LVDM179 Only