SMOMAPL138BGWTA3R

SMOMAPL138B低功耗应用处理器 SMOMAPL138B Low-Power Applications Processor

This device is a Low-power applications processor based on an ARM926EJ-S and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000 platform of DSPs.

This device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer RISC technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 CP15, protection module, and Data and program Memory Management Units MMUs with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag VIVT. The ARM core also has a 8KB RAM Vector Table and 64KB ROM.

The device DSP core uses a two-level cache-based architecture. The Level 1 program cache L1P is a 32KB direct mapped cache and the Level 1 data cache L1D is a 32KB 2-way set-associative cache. The Level 2 program cache L2P consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC EMAC with a Management Data Input/Output MDIO module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit I2C Bus interfaces; one multichannel audio serial port McASP with 16 serializers and FIFO buffers; two multichannel buffered serial ports McBSP with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable one configurable as watchdog; a configurable 16-bit host port interface HPI ; up to 9 banks of 16 pins of general-purpose input/output GPIO with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces each with RTS and CTS; two enhanced high-resolution pulse width modulator eHRPWM peripherals; 3 32-bit enhanced capture eCAP module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator APWM outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface EMIFA for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller.

The Ethernet Media Access Controller EMAC provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second Mbps and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output MDIO interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces.

The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I 1.5 Gbps and SATA II 3.0 Gbps.

The Universal Parallel Port uPP provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters.

A Video Port Interface VPIF is included providing a flexible video input/output port.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

This device has a complete set of development tools for the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.