SM320DM642AZDKI7
SM320DM642 - HiRel它的视频/影像定点数字信号处理器 SM320DM642-HiRel Video/Imaging Fixed Point Digital Signal Processor
* Controlled Baseline * One Assembly/Test/Fabrication Site * Enhanced Diminishing Manufacturing Sources DMS Support * Enhanced Product-Change Notification * Qualification Pedigree1 * High-Performance Digital Media Processor * 2 ns, 1.67 ns, 1.39 ns Instruction Cycle Time * 720 MHz Clock Rate 500/600 MHz devices are product preview only * Eight 32-Bit Instructions/Cycle * 5760 MIPS * Fully Software-Compatible With C64x™ * Veloci.2™ Extensions to VelociTI™ Advanced Very Long Instruction Word VLIW TMS320C64x™ DSP Core * Eight Highly Independent Functional Units With VelociTI.2™ Extensions: * Six ALUs 32/40 Bit, Each Supports Single 32 Bit, Dual 16 Bit, or Quad 8 Bit Arithmetic per Clock Cycle * Two Multipliers Support Four 16 × 16-Bit Multiplies 32 Bit Results per Clock Cycle or Eight 8 × 8 Bit Multiplies 16 Bit Results per Clock Cycle * Load-Store Architecture With Non-Aligned Support * 64 32-Bit General-Purpose Registers * Instruction Packing Reduces Code Size * All Instructions Conditional * Instruction Set Features * Byte Addressable 8/16/32/64 Bit Data * 8-Bit Overflow Protection * Bit Field Extract, Set, Clear * Normalization, Saturation, Bit-Counting * VelociTI.2™ Increased Orthogonality * L1/L2 Memory Architecture * 128K Bit 16K Byte L1P Program Cache Direct Mapped * 128K Bit 16K Byte L1D Data Cache 2-Way Set-Associative * 2M Bit 256K Byte L2 Unified Mapped RAM/Cache Flexible RAM/Cache Allocation * Endianess: Little Endian, Big Endian * 64 Bit External Memory Interface EMIF * Glueless Interface to Asynchronous Memories SRAM and EPROM and Synchronous Memories SDRAM, SBSRAM, ZBT SRAM, and FIFO * 1024M-Byte Total Addressable External Memory Space * Enhanced Direct-Memory-Access EDMA Controller 64 Independent Channels * 10/100 Mbps Ethernet MAC EMAC * IEEE 802.3 Compliant * Media Independent Interface MII * Eight Independent Transmit TX Channels and One Receive RX Channel * Management Data Input/Output MDIO * Three Configurable Video Ports * Provide a Glueless I/F to Common Video Decoder and Encoder Devices * Supports Multiple Resolutions/Video Stds * VCXO Interpolated Control Port VIC * Supports Audio/Video Synchronization * Host Port Interface HPI [32/16 Bit] * 32 Bit/66 MHz, 3.3-V Peripheral Component Interconnect PCI Master/Slave Interface Conforms to PCI Specification 2.2 * Multichannel Audio Serial Port McASP * Eight Serial Data Pins * Wide Variety of I2S and Similar Bit Stream Format * Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats * Inter-Integrated Circuit I2C Bus™ * Two Multichannel Buffered Serial Ports McBSPs * Three 32 Bit General Purpose Timers * Sixteen General Purpose I/O GPIO Pins * Flexible PLL Clock Generator * IEEE-1149.1 JTAG Boundary-Scan-Compatible * 548 Pin Ball Grid Array BGA Package, 0.8 mm Ball Pitch * 0.13 µm/6 Level Cu Metal Process CMOS * 3.3 V I/O, 1.4 V Internal A-500, A-600, -600, -720