MC100LVEL29DWR2G
数据手册.pdf3.3V ECL双差分数据和时钟D触发器有设定和复位 3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset
2 元件 D 型 1 位 正边沿 20-SOIC(0.295",7.50mm 宽)
立创商城:
MC100LVEL29DWR2G
得捷:
IC FF D-TYPE DUAL 1BIT 20SOIC
艾睿:
Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 2-Element 20-Pin SOIC W T/R
安富利:
Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 2-Element 20-Pin SOIC W T/R
Chip1Stop:
Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 2-Element 20-Pin SOIC W T/R
Verical:
Flip Flop D-Master-Slave Type Pos-Edge/Neg-Edge 2-Element 20-Pin SOIC W T/R
Win Source:
3.3V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset