锐单电子商城 , 一站式电子元器件采购平台!
  • 电话:400-990-0325

MC100EP139DWG

MC100EP139DWG

数据手册.pdf
ON Semiconductor(安森美) 电子元器件分类

3.3/5V ECL ÷2/4,÷4/5/6 时钟发生芯片

The MC10/100EP139 is a low skew divide by 2/4, divide by 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the V output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the V output should be connected to the CLKbar input and bypassed to ground via a 0.01uF capacitor.The common enable ENbar is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset MR input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the divide by 2/4 and the divide by 4/5/6 outputs of a single device. All V pins must be externally connected to power supply to guarantee proper operation.The 100 Series contains temperature compensation.

Features

---

 |

.
Maximum Frequency >1.0 GHz Typical
.
50ps Output-to-Output Skew
.
PECL Mode Operating Range: VCC=3.0 V to 5.5 V with VEE = 0 V
.
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
.
Open Input Default State
.
Safety Clamp on Inputs
.
Synchronous Enable/Disable
.
Master Reset for Synchronization of Multiple Chips
.
VBB Output
.
Pb-Free Packages are Available
MC100EP139DWG中文资料参数规格
技术参数

频率 1 GHz

电源电压DC 3.00V min

无卤素状态 Halogen Free

输出接口数 4

供电电流 83.0 mA

电路数 1

工作温度Max 85 ℃

工作温度Min -40 ℃

电源电压 3V ~ 5.5V

电源电压Max 5.5 V

电源电压Min 3 V

封装参数

安装方式 Surface Mount

引脚数 20

封装 SOIC-20

外形尺寸

封装 SOIC-20

物理参数

工作温度 -40℃ ~ 85℃

其他

产品生命周期 Active

包装方式 Tube

制造应用 Low-Clock Skew Generation

符合标准

RoHS标准 RoHS Compliant

含铅标准 Lead Free

REACH SVHC版本 2015/12/17

海关信息

ECCN代码 EAR99

MC100EP139DWG引脚图与封装图
MC100EP139DWG引脚图

MC100EP139DWG引脚图

MC100EP139DWG封装图

MC100EP139DWG封装图

MC100EP139DWG封装焊盘图

MC100EP139DWG封装焊盘图

在线购买MC100EP139DWG
型号 制造商 描述 购买
MC100EP139DWG ON Semiconductor 安森美 3.3/5V ECL ÷2/4,÷4/5/6 时钟发生芯片 搜索库存
替代型号MC100EP139DWG
图片 型号/品牌/封装 代替类型 描述 替代型号对比

型号: MC100EP139DWG

品牌: ON Semiconductor 安森美

封装: SOIC-W 1GHz 3V 20Pin

当前型号

3.3/5V ECL ÷2/4,÷4/5/6 时钟发生芯片

当前型号

型号: MC100EP139DWR2G

品牌: 安森美

封装: SOIC-W

完全替代

3.3V / 5V ECL ± 2/4, ±4 /5/6时钟发生器芯片 3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation Chip

MC100EP139DWG和MC100EP139DWR2G的区别

型号: MC100LVEL14DWR2G

品牌: 安森美

封装: SOIC-W

类似代替

3.3V ECL 1 : 5时钟分配芯片 3.3V ECL 1:5 Clock Distribution Chip

MC100EP139DWG和MC100LVEL14DWR2G的区别

型号: MC10EP139DWR2G

品牌: 安森美

封装: SOIC-W

类似代替

3.3V / 5V ECL ± 2/4, ±4 /5/6时钟发生器芯片 3.3V / 5V ECL ±2/4, ±4/5/6 Clock Generation Chip

MC100EP139DWG和MC10EP139DWR2G的区别