LMK04208NKDR

具有 6 个可编程输出的超低噪声时钟抖动消除器 64-WQFN -40 to 85

The LMK04208 is a high performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture is capable of 111 fs, RMS jitter 12 kHz to 20 MHz using a low-noise VCXO module or sub-200 fs rms jitter 12 kHz to 20 MHz using a low cost external crystal and varactor diode.

The dual loop architecture consists of two high-performance phase-locked loops PLL, a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator VCO. The first PLL PLL1 provides low-noise jitter cleaner functionality while the second PLL PLL2 performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When paired with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise offsets below 50 kHz of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise offsets above 50 kHz where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.