LMK04806BISQE/NOPB

时钟发生器, 抖动滤除器, 500MHZ, 3.15 V至3.45 V, 12输出, WQFN-64

The is a highest-performance Clock Conditioner with superior clock jitter cleaning, generation and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum architecture is capable of 111fs RMS jitter 12kHz to 20MHz using a low noise VCXO module or sub-200fs RMS jitter 12kHz to 20MHz using an external crystal and varactor diode. The dual loop architecture consists of two high-performance phase-locked loops PLL, a low-noise crystal oscillator circuit and a high-performance voltage controlled oscillator VCO. The first PLL PLL1 provides low-noise jitter cleaner functionality while the second PLL PLL2 performs the clock generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tuneable crystal and varactor diode.

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Ultra-low RMS jitter performance

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Dual loop PLLatinum™ PLL architecture

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Integrated low-noise crystal oscillator circuit

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Holdover mode when input clocks are lost

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Automatic or manual triggering/recovery

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2 Redundant input clocks with LOS

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12 LVPECL, LVDS or LVCMOS Programmable outputs

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Digital delay - Fixed or dynamically adjustable

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25ps Step analogue delay control

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Three default clock outputs at power up

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Multi-mode - Dual PLL, single PLL and clock distribution

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Green product and no Sb/Br

Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.