LMH0031VS/NOPB

具有视频和辅助数据 FIFO 的数字视频解串器/解码器 64-TQFP 0 to 70

The is a Digital Video Deserializer/Descrambler with video and ancillary data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps or 1.483Gbps serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M proposed 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 includes clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, ancillary data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods.

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SDTV/HDTV serial digital video standard compliant

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Uses 27MHz crystal or clock oscillator reference

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Fast VCO lock time of <500µs at 1.485Gbps

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Built-in self-test BIST and video test pattern generator TPG patent applications made or pending

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Automatic EDH/CRC word and flag processing

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Adjustable, 4-deep parallel output video data FIFO

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Flexible control and configuration I/O port

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LVCMOS compatible control inputs and clock and data outputs

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LVDS and ECL-Compatible, differential and serial inputs

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Green product and no Sb/Br