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JTAG-HS2
Digilent 迪芝伦 电子元器件分类

DIGILENT  JTAG-HS2  编程电缆, JTAG, 用于XILINX FPGA

The is a high speed programming solution for Xilinx field programmable gate arrays FPGAs. The cable is fully compatible with all Xilinx tools and can be seamlessly driven from iMPACT, Chip Scope, and EDK. The HS2 attaches to target boards using 6 pin, 100mil spaced programming header or Xilinx"s 2x7, 2mm connector and the included adaptor. The PC powers the JTAG-HS2 through the USB port and will recognize it as a programming cable when connected to a PC, even if the cable is not attached to the target board. The HS2 has a separate Vdd pin to supply the JTAG signal buffers. The high speed 24mA three state buffers allow target boards to drive the HS2 with signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. To function correctly the HS2"s Vdd pin must be tied to the same voltage supply that drives the JTAG port on the FPGA.

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Small, complete, all in one JTAG programming solution for Xilinx FPGAs
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Compatible with IEEE 1149.7-2009 class T0 to class T4 includes 2 wire JTAG
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Separate Vref drives JTAG/SPI signal voltages, Vref can be any voltage between 1.8V and 5V
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High speed USB 2 port that can drive JTAG/SPI bus at up to 30Mbit/sec
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JTAG/SPI frequency settable by user
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Uses micro AB USB 2 connector
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SPI programming solution modes 0 and 2 up to 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec
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Fully supported by the Adept SDK, allowing custom JTAG/SPI applications to be created
JTAG-HS2中文资料参数规格
其他

附件类型 Programming Cable

用于 Xilinx FPGAs

特点 Compatible with IEEE 1149.7-2009 Class T0 - Class T4

产品范围 \-

SVHC高度关注物质 No SVHC 17-Dec-2015

制造应用 Embedded Design & Development, 嵌入式设计与开发

符合标准

RoHS标准 RoHS Compliant

REACH SVHC标准 No SVHC

REACH SVHC版本 2015/12/17

JTAG-HS2引脚图与封装图
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