IS42S16400B-6TL

DRAM Chip SDRAM 64Mbit 4Mx16 3.3V 54Pin TSOP-II

OVERVIEW

ISSI"s 64Mb Synchronous DRAM IS42S16400B is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.

FEATURES

• Clock frequency: 166, 143 MHz

• Fully synchronous; all signals referenced to a positive clock edge

• Internal bank for hiding row access/precharge

• Single 3.3V power supply

• LVTTL interface

• Programmable burst length

– 1, 2, 4, 8, full page

• Programmable burst sequence: Sequential/Interleave

• Self refresh modes

• 4096 refresh cycles every 64 ms

• Random column address every clock cycle

• Programmable CASlatency 2, 3 clocks

• Burst read/write operations capability

• Burst termination by burst stop and precharge command

• Byte controlled by LDQM and UDQM

• Industrial temperature availability

• Package:400-mil 54-pin TSOP II

• Lead-free package is available