IS61NLF102418-6.5TQ

SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 6.5ns 100Pin TQFP

* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 100-pin TQFP package * Power Supply: Vdd 3.3V ± 5%, Vddq 3.3V/2.5V ± 5% * JTAG Boundary Scan for PBGA packages * Commercial and Industrial temperature available * Lead-free available