IS61NLP102418-250B3

SRAM Chip Sync Dual 3.3V 18M-Bit 1M x 18 2.6ns 165Pin FBGA

* 100 percent bus utilization * No wait cycles between Read and Write * Internal self-timed write cycle * Individual Byte Write Control * Single Read/Write control pin * Clock controlled, registered address, data and control * Interleaved or linear burst sequence control using MODE input * Three chip enables for simple depth expansion and address pipelining * Power Down mode * Common data inputs and data outputs * CKE pin to enable clock and suspend operation * JEDEC 100-pin TQFP, 119-ball PBGA, 165-ball PBGA and 209-ball x72 PBGA packages * Power supply: VDD 3.3V ± 5%, VDDQ 3.3V/2.5V ± 5% * JTAG Boundary Scan for PBGA packages * Industrial temperature available * Lead-free available * Leaded option available upon request