FDC6322C

双N和P通道FET数字 Dual N & P Channel , Digital FET

General Description

These dual N & P Channel logic level enhancement mode field effec transistors are produced using "s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors.

Features

■ N-Ch 25 V, 0.22 A, RDSON = 5 W @ VGS= 2.7 V.

■ P-Ch 25 V, -0.46 A, RDSON = 1.5 W @ VGS= -2.7 V.

■ Very low level gate drive requirements allowing direct operation in 3 V circuits. VGSth < 1.5 V.

■ Gate-Source Zener for ESD ruggedness.

   >6kV Human Body Model

■ Replace NPN & PNP digital transistors.