EPM7128AETC100-5

CPLD - 复杂可编程逻辑器件 CPLD - MAX 7000 128 Macro 84 IOs

Description

The MAX 7000 family of high-density, high-performance PLDs is based on ’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP,pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest Group PCI SIG PCI Local Bus Specification, Revision 2.2. See Table 3 for available speed grades.

Features

■ High-performance, EEPROM-based programmable logic devices PLDs based on second-generation MAX®architecture

■ 5.0-V in-system programmabilityISP through the built-in IEEE Std. 1149.1 Joint Test Action Group JTAG interface available in MAX 7000S devices

– ISP circuitry compatible with IEEE Std. 1532

■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices

■ Built-in JTAG boundary-scan test BST circuitry in MAX7000S devices with 128 or more macrocells

■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates see Tables 1and 2

■ 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies including interconnect

■ PCI-compliant devices available