CDCF2509

3.3V 锁相环时钟驱动器

The is a high-performance, low-skew, low-jitter, phase-lock loop PLL clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback FBOUT output to the clock CLK input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control 1G and 2G inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

The CDCF2509 is characterized for operation from 0°C to 85°C.

For application information refer to application reports _High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516_ literature number SLMA003 and _Using CDC2509A/2510A PLL with Spread Spectrum Clocking SSC_ literature number SCAA039.

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Use _CDCVF2509A_ as a Replacement for this Device

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Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9

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Spread Spectrum Clock Compatible

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Operating Frequency 25 MHz to 140 MHz

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Static Phase Error Distribution at 66 MHz to 133 MHz is ±125 ps

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Jitter cyc-cyc at 66 MHz to 133 MHz Is |70| ps

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Available in Plastic 24-Pin TSSOP

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Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications

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Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs

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Separate Output Enable for Each Output Bank

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External Feedback FBIN Terminal Is Used to Synchronize the Outputs to the Clock Input

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On-Chip Series Damping Resistors

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No External RC Network Required

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Operates at 3.3 V