CY7C1460KV33-167BZC

SRAM Chip Sync Quad 3.3V 36M-Bit 1M x 36 3.4ns 165Pin FBGA Tray

SRAM - 同步，SDR 存储器 IC 36Mb（1M x 36） 并联 165-FBGA（15x17）

立创商城:
CY7C1460KV33-167BZC

艾睿:
PIPELINED SRAM WITH NOBL ARCHITECTURE WITH ECC, 36-MBIT, 1 M X 36/2 M X 18

安富利:
The CY7C1460KV33 are 3.3 V, 1M × 36 synchronous pipelined burst SRAMs with No Bus Latency™ NoBL™ logic, respectively. They are designed to support unlimited true back-to-back read/write operations with no wait states. The CY7C1460KV33 devices are equipped with the advanced NoBL logic required to enable consecutive read/write operations with data being transferred on every clock cycle. 6This feature dramatically improves the throughput of data in systems that require frequent write and read transitions. The CY7C1460KV33 devices are pin-compatible and functionally equivalent to ZBT devices.All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the clock enable CEN\\ signal, which when deasserted suspends operation and extends the previous clock cycle.Write operations are controlled by the byte write selects BWa\–BWd\ for CY7C1460KV33 and a write enable WE\\ input. All writes are conducted with on-chip synchronous self-timed write circuitry.Three synchronous chip enables CE1\, CE2\, and CE3\\ and an asynchronous output enable OE\\ enable easy bank selection and output tristate control. To avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence.