CY7C1356A-100AC

256K ×36 / 512K ×18的SRAM流水线与NoBL⑩架构 256K x 36/512K x 18 Pipelined SRAM with NoBL⑩ Architecture

Functional Description

The CY7C1354A and CY7C1356A SRAMs are designed to eliminate dead cycles when transitioning from Read to Write or vice versa. These SRAMs are optimized for 100% bus utilization and achieve Zero Bus Latency™ ZBL™/No Bus Latency™ NoBL™. They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. These employ high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.

Features

• Zero Bus Latency™, no dead cycles between Write and Read cycles

• Fast clock speed: 200, 166, 133, 100 MHz

• Fast access time: 3.2, 3.6, 4.2, 5.0 ns

• Internally synchronized registered outputs eliminate the need to control OE

• Single 3.3V –5% and +5% power supply VCC

• Separate VCCQ for 3.3V or 2.5V I/O

• Single WEN Read/Write control pin

• Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications

• Interleaved or linear four-word burst capability

• Individual byte Write BWa–BWd control may be tied LOW

• CEN pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Automatic power-down feature available using ZZ mode or CE select

• JTAG boundary scan

• Low-profile 119-bump, 14-mm × 22-mm BGA Ball Grid Array, and 100-pin TQFP packages