CY7C1460KV33-200AXC

SRAM Chip Sync Quad 3.3V 36M-Bit 1M x 36 3.2ns 100Pin TQFP Tray

* Pin-compatible and functionally equivalent to Zero Bus Turnaround ZBT™ * Supports 250-MHz bus operations with zero wait states * Available speed grades are 250, 200, and 167 MHz * Internally self-timed output buffer control to eliminate the need to use asynchronous OE\ * Fully-registered inputs and outputs for pipelined operation * Byte write capability * 3.3-V power supply * 3.3-V/2.5-V I/O power supply * Fast clock-to-output time * 2.5 ns for 250-MHz device * Clock enable CEN\\\\ pin to suspend operation * Synchronous self-timed writes * CY7C1460KV33 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA packages * IEEE 1149.1 JTAG-compatible boundary scan * Burst capability—linear or interleaved burst order * “ZZ” sleep mode option * On-chip Error Correction Code ECC to reduce Soft Error Rate SER