CK-V7-VC7215-G

表征套件, Virtex-7 FPGA, IBERT, GTH收发器评估, Vivado

The from is a Virtex-7 FPGA VC7215 characterization kit. The Virtex™-7 FPGA VC7215 characterization kit provides the hardware environment for characterizing and evaluating 80 GTH 13.1Gbps transceivers of the on-board Virtex-7 V690T FPGA. The VC7215 allows evaluation of the Integrated Bit Error Ratio Test IBERT demonstration using the Vivado design suite. Each GTH quad and its associated reference clock are routed from the FPGA to a connector pad which is designed to interface with a Samtec BullsEye connector. A cable enabled with a BullsEye connector and 10 standard SMAs allows users to connect to a broad range of evaluation platforms from backplanes and optical evaluation boards to high speed test equipment. Each BullsEye connector handles a full GTH quad, four transmit/receive pairs as well as the two independent reference clocks enabling the highest level of flexibility in testing custom applications.

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Hardware, design tools, IP and pre-verified reference designs

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Integrated Bit Error Ratio Test IBERT reference design

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System ACE™ SD controller, 693120 logic cell, 3600 DSP slices

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Expand I/O with 3 FPGA Mezzanine Card FMC interface

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BullsEye connector supporting a full GTH quad with four transmit/receive pairs

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Twenty Samtec BullsEye connector pads for the GTH transceivers and reference clocks

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Two pairs of differential MRCC inputs with SMA connectors

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Power status LEDs and general purpose DIP switches, LEDs, push buttons and test I/O display

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SuperClock-2 module supporting multiple frequencies, 52920Kb memory

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Fixed, 200MHz 2.5V LVDS oscillator wired to multi region clock capable MRCC inputs clocking