AD9513BCPZ

ANALOG DEVICES  AD9513BCPZ  芯片, 时钟分配器

The is a 3-output Clock Distribution IC emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800MHz in LVDS mode and to 250MHz in CMOS mode. Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment. One of the outputs features a delay element with three selectable full-scale delay values 1.8, 6.0 and 11.6ns, each with 16 steps of fine adjustment. The AD9513 does not require an external controller for operation or setup.

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Phase select for coarse delay adjust

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Device configured with 4-level logic pins

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Time delays up to 11.6ns

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Divide-by in range from 1 to 32

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1.6GHz Differential clock input

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3 Programmable dividers