74ACT11478

具有三态输出的亚稳电阻八路 D 类双组触发器

The is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization applications where the normal setup and hold time specifications are frequently violated.

Synchronization of two digital signals operating at different frequencies is a common system problem. This problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution, however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the setup or hold time specification is violated, the output response is uncertain.

A flip-flop is metastable if its output hangs up in the region between VIL and VIH. The metastable condition lasts until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum propagation delay.

The problem of metastability is typically solved by adding an additional layer of synchronization. This type of dual ranking is employed in the 74ACT11478. The probability of the second stage entering the metastable state is exponentially reduced by this dual-rank architecture. The 74ACT11478 provides a one-chip solution for system designers in asynchronous applications.

The 74ACT11478 is characterized for operation from - 40°C to 85°C.

 

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Inputs Are TTL-Voltage Compatible

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Specifically Designed for Data Synchronization Applications

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Improved Metastable Characteristics Provide Greater System Reliability

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3-State Outputs Drive Bus Lines Directly

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Flow-Through Architecture to Optimize PCB Layout

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Center-Pin VCC and GND Configurations to Minimize High-Speed Switching Noise

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EPICTM Enhanced-Performance Implanted CMOS 1-m Process

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500-mA Typical Latch-Up Immunity at 125°C

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Package Options Include Plastic Small Outline Packages and Standard Plastic 300-mil DIPs